Operations in certain semiconductor devices, such as dynamic random-access memory (DRAM), are typically driven according to an input clock cycle. In such devices, synchronizing, or “locking,” the input clock signal with the output signal may improve performance of the device by ensuring that timing between the device output and external components is synchronized. Traditional methods for synchronizing clock cycles include using a delay-locked loop (DLL). Generally, a DLL includes a variable chain of delay gates that can be applied to the signal in order to synchronize the internal clock with the external clock. Traditional methods include selecting a single step size (i.e. delay amount) and sequentially stepping the delay applied to the internal clock cycle and comparing the delayed internal clock cycle to the external clock in order to determine if the phases match.